Error 10327: Can't determine definition of operator ""+""

Hello,

I'm getting the same error that is mentioned many times in this topic..

Error (10327): VHDL error at ADD_SUBB.vhd(31): can't determine definition of operator ""+"" -- found 0 possible definitions

This is my code.. What am i doing wrong?

Already many thanks for your help! :)

-- Library Declaration

LIBRARY ieee;

USE ieee.numeric_std.all;

USE ieee.std_logic_1164.all;

-- Entity Declaration

entity ADD_SUBB is

port

(

a : in std_logic_vector (3 downto 0); -- Input A

b : in std_logic_vector (3 downto 0); -- Input B

sel : in std_logic; -- ADD/SUB, Go's to mux to choose if it is SUB or ADD.

r : out std_logic_vector (3 downto 0); -- Result of ADD or SUB

ovf : out std_logic; -- Overflow, when result is above 15

sign : out std_logic -- + or -

 );

end ADD_SUBB;

-- Architecture Body

architecture RTL of ADD_SUBB is

signal c : std_logic_vector (3 downto 0); -- sum of adder

signal d : std_logic; -- overflow of adder

signal e : std_logic_vector (3 downto 0); -- sum of subtractor

signal f : std_logic; -- sign bit +/-

Begin

process (a,b) -- Add function.

variable p: std_logic_vector (4 downto 0 );

begin

p := '0' & a + '0' & b;

c <= p(3 downto 0) after 5ns;

d <= p(4) after 5ns;

end process;

process(a,b) -- Sub function.

begin

p := '0' & a - '0' & b;

e <= p(3 downto 0) after 5ns;

f <= p(4) after 5ns;

end process;

process(c,d,e,f,sel) -- Decoder(mux)

begin

if sel = '1' then r <= c; ovf <= d;

else r <= e; sign <= f;

end if;

end process;

end architecture;