entity problem/errors with easy counter

Hello guys,

I am new to VHDL, but I am having some problem with my entitiy creation. The design below counts the number of leading zeros in a binary vector, starting

from the left end. But i am not able to compile my file at all thats why I need your help.

This is the error message I got:

Error (10500): VHDL syntax error at zero_counter.vhd(5) near text "ENTITY"; expecting "(", or "'", or "."

------------------------------------------------------------------

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.numeric_std.all

ENTITY zero_counter IS -- error message at this point

GENERIC (WID: Integer :=8;

Minval: unsigned:="0000_0000"

);

PORT(data: IN STD_LOGIC_VECTOR(WID-1 downto 0);

output: OUT STD_LOGIC_VECTOR(WID-1 downto 0)

);

END zero_counter;

ARCHITECTURE behavior OF zero_counter IS

BEGIN

PROCESS (data)

VARIABLE count: unsigned (0 to WID-1);

BEGIN

count := Minval;

FOR i IN 0 to Wid-1 LOOP

CASE data(i) IS

WHEN '0' => count := count + 1; -- data(i)='0' , count++

WHEN OTHERS => NEXT; --jump to next iteration

END CASE;

END LOOP;

output <= std_logic_vector(count);

END PROCESS;

END behavior;

-------------------------------

I already tryed to realize it without the generic block, but its all the same.

I am using Quartus 13.1

Can someone help me?