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Altera_Forum
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7 years ago

Encoder for dsd audio stream in SDIF-3 format, VHDL - help a newbie

Hello folks,

I'm a newbie in VHDL programming.

I'm trying to achieve SDIF-3 encoding from a dsd datastream coming off from an A-D conversion chip.

The dsd stream from the chip features two independent channels (L&R) data flow, plus a bitclock line.

The SDIF-3 coding scheme (see pic below), states that the channel coding splits each original bit in a 2 'semi-bit' pattern, by double the original bitclock rate.

IE: if the original bit on the source is '0', the pattern must include the original value+it's inverted, so '0-1',

if the bit value of the source stream is '1', the pattern is '10', and so on...

I was thinking of using a double-edge triggering to do the frequency doubling of the output stream, so that at the rising edge, the encoder outputs the first semi-bit value, then on the falling edge, the encoder outputs the inverted semi-bit to complete the pattern.

Please see the image attached below about the official coding scheme for this format.

I'm not sure if the code is correct, even if it is possible to do it that way.

Unfortunately I have lack of knowledge on how to simulate this.

Any help, suggestion, greatly appreciated. My code attached...

Thank you in advance! :)

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  • Altera_Forum's avatar
    Altera_Forum
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    7 years ago

    --- Quote Start ---

    Stay away from the XOR ... as I said oring it with a clock and then registering that with the same clock is fraught with possible issues; draw the timing diagram (carefully) and you will see why.

    Assume your clock is running at twice the bit-rate, and every '1'or '0' at the input lasts for 2 clock periods, you can write a (very simple) state machine to generate the correct code depending on the input received.

    --- Quote End ---

    Thanks!

    I changed the code following your suggestion. What I had in mind was treating the received input, output pattern forming register and output as 2-bit vectors,

    and using simple IF statements.

    However it doesn't seem to work. No pattern going on.

    New code and sim shot attached below.

    What am I doing wrong? :confused:

    Thank you!
  • Altera_Forum's avatar
    Altera_Forum
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    7 years ago

    Okay, I think I have something that probably works, I'm not sure if simulation is cheating me.

    With the new code, if Sim reset goes high at the falling edge, the encoder works fine, as you can see on sim1 pic attached.

    If reset goes high at the rising edge, the encoder does the pattern in reverse. (sim2 pic below).

    The CLK line is external, and runs at DDR, it's period is 10ns, so data period is 20ns.

    I've added a toggler to run the output at DDR, triggered at the rising edge.

    Is this a problem of simulation, what to do to make the encoder do the pattern right anytime?

    Any help appreciated!