Encoder for dsd audio stream in SDIF-3 format, VHDL - help a newbie

Okay, I think I have something that probably works, I'm not sure if simulation is cheating me.

With the new code, if Sim reset goes high at the falling edge, the encoder works fine, as you can see on sim1 pic attached.

If reset goes high at the rising edge, the encoder does the pattern in reverse. (sim2 pic below).

The CLK line is external, and runs at DDR, it's period is 10ns, so data period is 20ns.

I've added a toggler to run the output at DDR, triggered at the rising edge.

Is this a problem of simulation, what to do to make the encoder do the pattern right anytime?

Any help appreciated!