We commonly using assert to do checks on parameters during synthesis:
entity SomeEntity is
generic map
(
DATA_WIDTH : natural
);
port map
(
data : std_logic_vector(DATA_WIDTH-1 downto 0)
);
end entitiy;
architecture arch of SomeEntity is
begin
assert DATA_WIDTH < 10 report "Data widths larger than 10 are not supported" severity error;
end architecture;
We also use it to simple output a message about what was compiled for future reference.
entity SomeEntity is
generic map
(
CONFIG1 : complex_record_type
);
port map
(
-- some ports
);
end entitiy;
architecture arch of SomeEntity is
function complex_enable_check(config: complex_record_type) return boolean is
begin
-- A complex function here that return a boolean based on a complex configuration record
end function;
begin
assert false report "Config1 value1 is " & integer'image(CONFIG1.value1) severity note;
assert false report "Config1 value2 is " & integer'image(CONFIG1.value2) severity note;
genBlock: if complex_enable_check(CONFIG1 ) generate
assert false report "<Design block name> is enabled" severity note;
-- Design block here
end generate;
end architecture;
We use complex record types and function in many place in our design that enable different blocks of code and it's useful to be able to output their values and results during synthesis. This allows us to look back at the message outputs when we have problems to help figure out the problem. Some of the function we use are hundreds of line of VHDL and many of our configuration type are records with many layer of nested records and arrays, so it's often not easy to understand what is happening without assert statements.
Any suggestions you have for alternatives would be appreciated.
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