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jkhoo
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
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EMIF link project error in Quartus 18.0

I am encountering error while running EMIF toolkit on quartus 18.1. the error are as follow: Prior to running this, i selected option-1 in the diagnostics tab of DDR3 SRAM Controller with Uniphy In...
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  • jkhoo's avatar
    jkhoo
    2 years ago

    Hi Adzim,

    Error message (0x80070005) was resolved by enabling JTAG server apps to communicate through "Private" and "Public" profile in Windows Defender Firewall.

    After resolving this Error message (0x80070005), I still face the same issue of executing:

    "{C:/intelfpga/18.1/quartus//../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt"

    I eventually figure out that Quartus Prime 18.1 std can't work with wsl (windows subsystem for linux).

    (The reason i enabled wsl in the first place was because i have both Quartus P 18.1 std and 22.1 in the same PC. And Quartus P 22.1 need WSL to compile ddr3 ip.)

    So i resolved the ddr3 IP compilation by unchecking Windows Subsystem for Linus in Windows Features.

jkhoo's avatar
jkhoo
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Hi Adzim,

I just verified and the device is the same.

I also saw another failure when generating the DDR IP.

below is the error i am encountering:

<html>Info: "<b>MyDDR3_master</b>" instantiated <b>altera_mem_if_ddr3_phy_core</b> "<b>p0</b>"
<html>Info: "<b>MyDDR3_master</b>" instantiated <b>altera_mem_if_ddr3_afi_mux</b> "<b>m0</b>"
Error: Error during execution of "{C:/intelfpga/18.1/quartus//../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally
Error: Execution of command "{C:/intelfpga/18.1/quartus//../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt" failed
Error: Authorized application C:\intelFPGA\18.1\quartus\bin64\jtagserver.exe is disabled in the firewall.
Error: Add failed: 0x80070005
Error: WindowsFirewallAddApp failed: 0x80070005
Error: ]2;Altera Nios II EDS 18.1 [gcc4]C:/intelfpga/18.1/quartus//bin64/uniphy_mcc -ac_code sequencer_mc/ac_rom.s -inst_code sequencer_mc/inst_rom.s -ac_rom ../MyDDR3_master_s0_AC_ROM.hex -inst_rom ../MyDDR3_master_s0_inst_ROM.hex -header sequencer/sequencer_auto.h -vheader ../sequencer_auto_h.sv -ac_rom_init sequencer/sequencer_auto_ac_init.c -inst_rom_init sequencer/sequencer_auto_inst_init.c -DAC_ROM_USER_ADD_0=0_0000_0000_0000 -DAC_ROM_USER_ADD_1=0_0000_0000_1000 -DAC_ROM_MR0=0100001000001 -DAC_ROM_MR0_CALIB= -DAC_ROM_MR0_DLL_RESET=0100101000000 -DAC_ROM_MR1=0000000000100 -DAC_ROM_MR1_OCD_ENABLE= -DAC_ROM_MR2=0001001011000 -DAC_ROM_MR3=0000000000000 -DAC_ROM_MR0_MIRR=0100000100001 -DAC_ROM_MR0_DLL_RESET_MIRR=0100010100000 -DAC_ROM_MR1_MIRR=0000000000100 -DAC_ROM_MR2_MIRR=0001000111000 -DAC_ROM_MR3_MIRR=0000000000000 -DQUARTER_RATE=0 -DHALF_RATE=1 -DFULL_RATE=0 -DNON_DES_CAL=0 -DAP_MODE=0 -DGUARANTEED_READ_BRINGUP_TEST=0 -DMEM_ADDR_WIDTH=13 -DHARD_PHY=0