Elaboration error in Merlin router

Hello,

I am having an issue with elaborating generated files from a Platform Designer project. I inherited a CPU project and needed to add interfaces to it so I could connect it to other Avalon bus designs in my project. I intended to add three Avalon MM Slave Translators which are in the picture below as application_interface, dai, and ddi.

However, anytime I add a new module to this project, generate HDL, and try to run Analysis & Synthesis I get the following error messages:

Info (12128): Elaborating entity "cpu_altera_merlin_router_181_wpeblfi" for hierarchy "gvrd:gvrd_0|cpu:CPU_INST|cpu_altera_mm_interconnect_181_nbk4cfi:mm_interconnect_0|cpu_altera_merlin_router_181_wpeblfi:router" File: /home/jdoher ty/ddm/exe_rh_icb_fw/hdl/lib_euresys_ip/gvrd-a10gx-tpg-fb_fifo/cpu/cpu/altera_mm_interconnect_181/synth/cpu_altera_mm_interconnect_181_nbk4cfi.v Line: 2552

Error (10232): Verilog HDL error at cpu_altera_merlin_router_181_wpeblfi.sv(208): index 32 cannot fall outside the declared range [31:0] for vector "address" File: /home/jdoherty/ddm/exe_rh_icb_fw/hdl/lib_euresys_ip/gvrd-a10gx-tpg-f b_fifo/cpu/cpu/altera_merlin_router_181/synth/cpu_altera_merlin_router_181_wpeblfi.sv Line: 208

Error (12152): Can't elaborate user hierarchy "gvrd:gvrd_0|cpu:CPU_INST|cpu_altera_mm_interconnect_181_nbk4cfi:mm_interconnect_0|cpu_altera_merlin_router_181_wpeblfi:router" File: /home/jdoherty/ddm/exe_rh_icb_fw/hdl/lib_euresys_ip/ gvrd-a10gx-tpg-fb_fifo/cpu/cpu/altera_mm_interconnect_181/synth/cpu_altera_mm_interconnect_181_nbk4cfi.v Line: 2552

If I remove the added interfaces and rebuild it once again passes elaboration.

I am using Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition which is a requirement for my project.

Has anyone seen this error before and is there any way to work around it?