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New Contributor

5 years ago

DPRAM IP configuration in Quartus 19.1 for Cyclone 10 implementation

Hi I am working of Quartus 19.1 lite and I want to make an implementation on device 10CL016YU484. There is a dpram in my design and I cannot access to all parameters to configure this block I want...

RichardT_altera

Super Contributor

5 years ago

Based on the UG, only ‘raddress’, ‘q_a’, or ‘q_b’ are available for asynchronous clear in the RAM 2-port IP parameters setting.

I don't think there is an option for asynchronous clear for the write clock domain.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ram_rom.pdf#page=30

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DPRAM IP configuration in Quartus 19.1 for Cyclone 10 implementation

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