DPRAM IP configuration in Quartus 19.1 for Cyclone 10 implementation

Hi

I am working of Quartus 19.1 lite and I want to make an implementation on device 10CL016YU484.

There is a dpram in my design and I cannot access to all parameters to configure this block

I want an asynch clear for write clock and an asynch clear for read clock, and I only can set an asynch clear for the read one.

How can I access the aynch clear for the write clock domain ?

Regards

Florent