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PSriv8's avatar
PSriv8
Icon for New Contributor rankNew Contributor
6 years ago

Do ROM and/or Lookup Tables introduce an additional delay to the overall circuit?

I want to design a circuit in which a 5-bit input In[4:0] (ranges from 0 to 31) is associated with a corresponding 3-bit output Out[2:0]. I can design this using a 8x3 Encoder in which 5 out of 8 inp...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi,

Do you have any updates? Can you see where the 8x3 encoder located in the Chip Planner?

Thanks.

Best regards,

KhaiY

PSriv8's avatar
PSriv8
Icon for New Contributor rankNew Contributor
6 years ago

Hi,

Thank you for replying me. I do not have the whole design yet, I am still writing codes for other modules for my design. Therefore I could not use the chip planner. However, I understood that whether I will be using the LUT as memory or as encoder, both will introduce delay in the circuit. Thank you for all your replies.

Warm Regards

Pallavi Srivastava