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PSriv8's avatar
PSriv8
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6 years ago

Do ROM and/or Lookup Tables introduce an additional delay to the overall circuit?

I want to design a circuit in which a 5-bit input In[4:0] (ranges from 0 to 31) is associated with a corresponding 3-bit output Out[2:0]. I can design this using a 8x3 Encoder in which 5 out of 8 inp...
PSriv8's avatar
PSriv8
Icon for New Contributor rankNew Contributor
6 years ago

Hi,

I am using only simulation to design my circuit, and I have written a code in Verilog for 8x3 encoder. I am not using existing 8x3 encoder in Intel FPGA.