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PSriv8's avatar
PSriv8
Icon for New Contributor rankNew Contributor
5 years ago

Do ROM and/or Lookup Tables introduce an additional delay to the overall circuit?

I want to design a circuit in which a 5-bit input In[4:0] (ranges from 0 to 31) is associated with a corresponding 3-bit output Out[2:0]. I can design this using a 8x3 Encoder in which 5 out of 8 inp...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,

Where do you implement the 8x3 encoder? Is it in the core logic? Are you using any Intel FPGA IP? If it is in the core logic, the 8x3 encoder is using the LUT as well.

Thanks.

Best regards,

KhaiY