Forum Discussion
Fuad1
New Contributor
New ContributorDMA controller Intel FPGA IP
To whom it may concern, I'm planning to use the Intel DMA controller FPGA IP (Avalon DMA) in my Cyclone V design. In this DMA IP documentation (chapter 30 of the document provided by the link below)...
sstrell
Super Contributor
Super ContributorThat's weird because EOP only makes sense in the context of Avalon streaming, not memory mapped. There's no parameter to use streaming instead of memory-mapped, so it's unclear what is being referred to.
