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Balaji_G_Intel's avatar
Balaji_G_Intel
Icon for New Contributor rankNew Contributor
7 years ago

DLATCH inferred as combinational loop on a specific condition

Warning (332125): Found combinational loop of 2 nodes File...

Warning (335091): The Timing Analyzer found 1 latches that cannot be analyzed as synchronous elements. For more details, run the Check Timing command in the Timing Analyzer or view the "User-Specified and Inferred Latches" table in the Synthesis report.

One of the condition the dlatch is not included as part of timing node for analysis, instead its treated as combinational loop

I have a specific testcase to reproduce. Please connect with me directly and i can provide the test case.

5 Replies

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    7 years ago

    Can you provide the RTL code? It sounds like you've accidentally inferred one or more latches in your design, which should be avoided.

    #iwork4intel

    • Balaji_G_Intel's avatar
      Balaji_G_Intel
      Icon for New Contributor rankNew Contributor
      7 years ago

      As its a internal case, Please send a email and i'll share qar directly.

  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    Icon for Regular Contributor rankRegular Contributor
    7 years ago

    Hi,

    I have sent an email to you. Please let me know if you did not received.

    Thanks.