Forum Discussion
Balaji_G_Intel
New Contributor
7 years agoDLATCH inferred as combinational loop on a specific condition
Warning (332125): Found combinational loop of 2 nodes File... Warning (335091): The Timing Analyzer found 1 latches that cannot be analyzed as synchronous elements. For more details, run the Check T...
KhaiChein_Y_Intel
Regular Contributor
7 years agoHi,
Can you share the design.qar to reproduce the error?
Thanks.
Balaji_G_Intel
New Contributor
7 years agoAs its a internal case, Please send a email and i'll share qar directly.