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AEsqu's avatar
AEsqu
Icon for Contributor rankContributor
5 years ago

Disable Quartus timing analyzer inverted clock

Hello, Is there a way to disable the inverted clock latch analysis in quartus 20.1 for arria 10? I had no such inverted clock analysis with the same design using Quartus 13.1 on stratix 3 , wit...
KennyT_altera's avatar
KennyT_altera
Icon for Super Contributor rankSuper Contributor
5 years ago

We can't confirm on this. As we do not do benchmark for old device e.g. Stratix III.


What you can do is open up the timing analyzer to do the comparison. It should show you all the details there.


I would suggest you attend the timing closure class as well. Look into the prerequisite before attending the timing closure class, as you might need to know on timing analyzer as well.


https://www.intel.com/content/www/us/en/programmable/support/training/course/odswtc02.html

Thanks


    • AEsqu's avatar
      AEsqu
      Icon for Contributor rankContributor
      5 years ago

      Unfortunately the bad hold timing violation plague is back using a new netlist of synplify pro.

      I don't know what quartus is doing anymore.

      Why is it adding +12 ns mlab routing all around the fpga ...