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Altera_Forum's avatar
Altera_Forum
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17 years ago

Disable pin count error for simulation in QuartusII 8.0

How can I make Quartus shut up and compile when I'm trying to compile a part of my design for simulation purposes, it gives me an error about the design having too many pins for the device I have selected. I just want to simulate this part, those pins are intended for internal connections. This is QuartusII 8.0 and I'm using block diagram entry.

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Use virtual pins for all top-level ports of this portion of the design that are not device pins in the full design and that are not a clock. The assignment for this is in the Assignment Editor. Virtual pins are documented in the Quartus handbook.

    Virtual pins are meant for compiling one portion of the design for bottom-up incremental compilation. I don't know whether you'll run into any simulation issues with them.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Can't you comment out those signals in the entity or even those parts of your design?

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Another option would be to use modelsim to simulate, then you can access any signal.

    //Ola
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    --- Quote Start ---

    Another option would be to use modelsim to simulate...

    --- Quote End ---

    The original poster is "using block diagram entry", which can't be simulated directly with ModelSim. The .bdf file(s) would need to be converted to VHDL or Verilog using "File --> Create / Update --> Create HDL Design File for Current File".

    I forgot that there are more virtual-pin restrictions than just the clock input. The Quartus handbook lists which ports can't use the virtual-pin assignment.