Forum Discussion
Altera_Forum
Honored Contributor
17 years ago --- Quote Start --- Another option would be to use modelsim to simulate... --- Quote End --- The original poster is "using block diagram entry", which can't be simulated directly with ModelSim. The .bdf file(s) would need to be converted to VHDL or Verilog using "File --> Create / Update --> Create HDL Design File for Current File". I forgot that there are more virtual-pin restrictions than just the clock input. The Quartus handbook lists which ports can't use the virtual-pin assignment.