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Honored ContributorDifficulties in causing the vga to count from 0 to 799
Hi guys,
can someone help me figure out why this code does not function properly. counter_int_v and counter_int_h is what i want to get counting in modelsim but i am not able to figure out the problem. Found below is my code: Library ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.all; USE ieee.std_logic_arith.all; entity VHDL_uppgift_8 is port( reset_n, CLOCK_50 : in std_logic; KEY : in std_logic_vector(3 downto 0); -- to the VGA unit/block VGA_HS, VGA_VS, VGA_CLK : out std_logic; VGA_BLANK_N, VGA_SYNC_N : out std_logic; VGA_B, VGA_G, VGA_R : out std_logic_vector(7 downto 0) ); end VHDL_uppgift_8; architecture VGA_ARCH of VHDL_uppgift_8 is --Kanske mycket tydligare (robustare) att ha en X och en Y unsigned med range. En record kanske är overkill, men kul att använda (se VHDL boken sidan 81). --using record type to involve elements with different data types type HV_type is record H : INTEGER range 0 to 799; V : INTEGER range 0 to 524; end record; signal counter_int_h : hv_type; signal counter_int_v : hv_type; signal clk_25mhz : std_logic := '0'; signal KEY_internal : std_logic_vector(3 downto 0); signal x : std_logic_vector(8 downto 0):= "101000000"; --X'320'--; signal y : std_logic_vector(7 downto 0):= "11110000"; --Y'240'--; begin VGA_CLK <= clk_25mhz; -- dett var något med att en klocka skall ut till VGA kontrollerns, kolla med DE2 manualen KEY_internal <= NOT KEY; -- Process to divide clock by two counter-- process_clock_25mhz: process (clock_50) begin if rising_edge(clock_50) then clk_25mhz <= not clk_25mhz; end if; end process; process_coordinate : process (reset_n, clk_25mhz) begin if(reset_n = '0') then x <= "101000000"; --Starting value on X y <= "11110000"; --Starting value on Y else if rising_edge(clk_25mhz) then if KEY_internal (0) = '1' then x <= x + 1; end if; if KEY_internal(1) = '1' then x <= x - 1; end if; if KEY_internal(2) = '1' then y <= y + 1; end if; if KEY_internal(3) = '1' then y <= y - 1; end if; end if; end if; end process; -- Process to generate Hsync an Vsync process_sync_screen : process (clk_25mhz) begin if rising_edge(clk_25mhz) then if reset_n = '0' then -- The next day the reset has been changed to synchronous reset counter_int_h <= (others =>'0') ; counter_int_v <= (others =>'0'); -- Starting values for the outputs VGA_HS <= '1'; VGA_VS <= '1'; VGA_BLANK_N <= '1'; -- Pedroni says nblank and nsync must be kept at '1' and '0' respectively VGA_SYNC_N <= '0'; -- VGA_R <=(others =>'0'); VGA_G <=(others =>'0'); VGA_B <=(others =>'0'); else -- count h up -- Clock out RGB Pixel Row Data Horizontal Sync-- -- ------------------------------------__________-------- -- 0 639 659 755 799 if counter_int_h >= 799 then counter_int_h <= (others => '0'); else counter_int_h <= counter_int_h + 1; end if; -- HSync Generation ('0')-- -- ------------------------------------__________--- -- 0 659 755 if (counter_int_h <= 755) and (counter_int_h >= 659) then VGA_HS <= '0'; else VGA_HS <= '1'; end if; -- 480 Horizontal Sync (pixel rows) Vertical Sync -- ---------------------------------------_______---------- -- 0 480 493-494 524 if (counter_int_v >= 524) and (counter_int_h >= 707) then counter_int_v <= (others => '0'); elsif counter_int_h = 707 then counter_int_v <= counter_int_v + 1; end if; --VSync Generation ('0') -- -- ---------------------------------------_______---------- -- 0 493-494 if (counter_int_v <= 494) and (counter_int_v >= 493) then VGA_VS <= '0'; else VGA_VS <= '1'; end if; -- This is when blank will be low(active) if counter_int_h <= 639 then VGA_BLANK_N <= '1'; else VGA_BLANK_N <= '0'; end if; -- This is when sync will be low (active) if counter_int_v <= 479 then VGA_SYNC_N <= '1'; else VGA_SYNC_N <= '0'; end if; if((counter_int_h >= x and counter_int_h <= x+3) and (counter_int_v >= y and counter_int_v <= y+3) )then -- white color ---------------------------------- VGA_R <= "11111111"; VGA_G <= "11111111"; VGA_B <= "11111111"; else -- No color ------------------------------------- VGA_R <= "00000000"; VGA_G <= "00000000"; VGA_B <= "00000000"; end if; end if; end if; end process process_sync_screen; end VGA_ARCH;
