Different time for different data extraction from the same FIFO

OK, this is my code:

when s4 =>

if(wrclk'event and wrclk ='1') then

numberoftimestamp <= q_b; -- RAM output

send_state <=S5;

end if;

when s5 =>

if(wrclk'event and wrclk ='1') then

if wrempty ='0' then

if unsigned(numberoftimestamp) >000000 and forlooper < unsigned(numberoftimestamp) then

rdreq<='1';

send_state <= S6;

else

forlooper<="000000";

send_state <=S8;

end if;

else

send_state <=s7;

end if;

end if;

when S6 =>

if(wrclk'event and wrclk ='1') then

if q /= MACinput then

rdreq<='0';

forlooper <=forlooper +1;

send_state <= S7;

else

send_state <=S6;

end if;

end if;

when S7 =>

if(wrclk'event and wrclk ='1') then

MACinput<=q;

send_state <= S5;

end if;

when S8... The address of the RAM in incremented and the FSM state reset.

MACinput is the signal that I want always at the same time. I'm a beginner about the VHDL programming, so I apologize for stupid mistakes :)