Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Different PLLs' output phase controlling issue

Hello everyone:

I have a question about PLL need your help.

System description: There are 11 veneers, and there are two same FPGAs on each board. The input clocks for each FPGA are from same source through clock buffer chip.

Requirment: Can PLLs inside each FPGA output a clock with same phase or with a known phase? (Disregard the clock buffer chip's phase error and the hardware trace routing differance).

According my memory, the PLL output's phase is same as the input clock when the PLL works at normal mode, am i right?

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    According attached file, the input and output of PLL is phase aligned when pll is in normal mode.

    I want to know how acurately of this phase alignment? Or is this phase 100% aligned? Are there any jitter or skew error?

    I only found a tOUTJITTER in device datasheet, and this parameter is about "dedicated clock output period jitter", it seems not about internal clock!
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Regarding your requirement: Yes, it can. With a bit of uncertainty, of course.

    When in normal mode, the PLL compensates the clock distribution network delay.

    So, the actual PLL's output is ahead of the input clock; it's the clock at the register's clock input that is in phase with the input clock.

    There isn't much information regarding the internal timing parameters of the FPGA in the datasheets. Instead, you just have to properly constrain your design so that TimeQuest can analyse it.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    --- Quote Start ---

    Regarding your requirement: Yes, it can. With a bit of uncertainty, of course.

    When in normal mode, the PLL compensates the clock distribution network delay.

    So, the actual PLL's output is ahead of the input clock; it's the clock at the register's clock input that is in phase with the input clock.

    There isn't much information regarding the internal timing parameters of the FPGA in the datasheets. Instead, you just have to properly constrain your design so that TimeQuest can analyse it.

    --- Quote End ---

    Hello, rbugalho:

    Do you mean that is in phase with the input clock at every register's clock input?