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Altera_Forum
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13 years ago

Different PLLs' output phase controlling issue

Hello everyone: I have a question about PLL need your help. System description: There are 11 veneers, and there are two same FPGAs on each board. The input clocks for each FPGA are from sa...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

According attached file, the input and output of PLL is phase aligned when pll is in normal mode.

I want to know how acurately of this phase alignment? Or is this phase 100% aligned? Are there any jitter or skew error?

I only found a tOUTJITTER in device datasheet, and this parameter is about "dedicated clock output period jitter", it seems not about internal clock!