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Altera_Forum
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13 years ago

Different PLLs' output phase controlling issue

Hello everyone: I have a question about PLL need your help. System description: There are 11 veneers, and there are two same FPGAs on each board. The input clocks for each FPGA are from sa...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Regarding your requirement: Yes, it can. With a bit of uncertainty, of course.

When in normal mode, the PLL compensates the clock distribution network delay.

So, the actual PLL's output is ahead of the input clock; it's the clock at the register's clock input that is in phase with the input clock.

There isn't much information regarding the internal timing parameters of the FPGA in the datasheets. Instead, you just have to properly constrain your design so that TimeQuest can analyse it.