different answer in quartus and modelsim

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i have done a verilog code and do the functional simulation in quartus version 9, to see the functionality of the module.

but, actually i need to run using modelsim.

but the problem now is

the output from the quartus and modelsim is not the same. (really big different) although the same input given for both.

does anyone know why is it so?

what's cause the problem?

thanks for help.

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Hi,

did you run a functional simulation or a timing simulation with the Quartus build-in simulator ?

Kind regards

GPK

waiyung: thank you very much...yes, it work now..i didn't realize on the initial condition..thank you. its really help ;)

pletz: yes, i'm running functional simulation with quartus build in simulator, (vector waveform)

There are many possible reasons for getting different results.

Initial conditions are one of them, but you mostly get unknown 'U' output in Modelsim when you omit an initialization for a signal, that's not needed in synthesized code. The solution is to add an initial value (usually 0) to all signals, that aren't explicitely reset in the code.

A more difficult point are non-synthesizable constructs, that may still get reasonable results in simulation. Another possibility is equivocal code, that involves a race condition.

Finally timing issues in synthesized code may cause logic failure, it would be predicted by the timing analyzer in most causes.

Also the simulation stimulus can be different from the input signals faced by the real design.

A gate level (timing simulation) should be expected to behave more like the real hardware, and also indicate possible timing violations by 'X' output signals.

The Quartus built-in simulator partly behaves different from Modelsim, it e.g. knows about register initialization in Altera FPGA.

You'll find, that differences between simulation and synthesis are a common problem and discussed in text books and other literature verbosely.

Hi, I apologize if my question is really basic, but how would you assign initial conditions in quartus?

I am facing the same problem where my modelsim-altera simulation results do not match the quartus/fpga results.

For example, results of the altmult_add megafunction vary - some are same while others are different (for a chain of inputs to the megafunction).

Generous help will be highly appreciated.

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how would you assign initial conditions in quartus

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By using signal initializers in VHDL respectively an initial block in Verilog.

SIGNAL b : std_logic := '1';

Quartus is inferring the register power-up state from this statement. Because newer FPGA families' LEs don't have an asnychronous set input, it performs "NOT gate push-back", inverting the register in- and outputs. See the Quartus Software Handbook:

Volume I Design and Synthesis/Section II Design Guidelines/6. Recommended HDL Coding Styles/Coding Guidelines for Registers and Latches/Register Power-Up Values in Altera Devices

The same statement is also used in simulation.