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how would you assign initial conditions in quartus
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By using signal initializers in VHDL respectively an initial block in Verilog.
SIGNAL b : std_logic := '1';
Quartus is inferring the register power-up state from this statement. Because newer FPGA families' LEs don't have an asnychronous set input, it performs "NOT gate push-back", inverting the register in- and outputs. See the Quartus Software Handbook:
Volume I Design and Synthesis/Section II Design Guidelines/6. Recommended HDL Coding Styles/Coding Guidelines for Registers and Latches/Register Power-Up Values in Altera Devices
The same statement is also used in simulation.
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