different answer in quartus and modelsim

There are many possible reasons for getting different results.

Initial conditions are one of them, but you mostly get unknown 'U' output in Modelsim when you omit an initialization for a signal, that's not needed in synthesized code. The solution is to add an initial value (usually 0) to all signals, that aren't explicitely reset in the code.

A more difficult point are non-synthesizable constructs, that may still get reasonable results in simulation. Another possibility is equivocal code, that involves a race condition.

Finally timing issues in synthesized code may cause logic failure, it would be predicted by the timing analyzer in most causes.

Also the simulation stimulus can be different from the input signals faced by the real design.

A gate level (timing simulation) should be expected to behave more like the real hardware, and also indicate possible timing violations by 'X' output signals.

The Quartus built-in simulator partly behaves different from Modelsim, it e.g. knows about register initialization in Altera FPGA.

You'll find, that differences between simulation and synthesis are a common problem and discussed in text books and other literature verbosely.