different answer in quartus and modelsim

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i have done a verilog code and do the functional simulation in quartus version 9, to see the functionality of the module.

but, actually i need to run using modelsim.

but the problem now is

the output from the quartus and modelsim is not the same. (really big different) although the same input given for both.

does anyone know why is it so?

what's cause the problem?

thanks for help.

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Hi,

did you run a functional simulation or a timing simulation with the Quartus build-in simulator ?

Kind regards

GPK