Difference in actual VCCIO used on board and I/O standard selected in Quartus project

It doesn't sound like you have a problem - unless you are referring to a product that is already shipping... see below.

Make sure your Quartus project pin assignments match your hardware. In the 'Pin Planner' specify the operating voltage for each pin individually. Pins in banks 3 & 4 must be specified as "1.8 V", or another 1.8V compliant standard. Any signal connected to a pin in a 3.3V powered bank, specify accordingly. Do this regardless of any default setting.

Alternatively, if you wish to change the default I/O standard for the project, you can. Change it under 'Assignments' -> 'Device...'. Click on the 'Device and Pin Options...' and select the 'Voltage' option on the left. You can then change the default I/O standard to what you want - in your case 3.3V LVTTL or 3.3V LVCMOS.

If you're already shipping this design, having compiled it with the incorrect settings, then the only issue you have is that you've not specified your design correctly when you compiled it. This will not damage the device. It may mean the static timing analysis Quartus performed may not be representative of your design. However, you're operating the I/O at a higher voltage than specified. You're only likely to see better than predicted performance as a result.

Regards,

Alex

Hi Alex,

Thank you very much for your reply.

Unfortunately we are in final stage and might not be able to change Quartus design. Still I will check and if I will be permitted, will make correction.

I have few more questions here. Do you have idea how threshold values are being calculated? I mean how FPGA decides what threshold value to be used to decide between '0' and '1'. Is it be according to I/O standard selected in Quartus pin planner ( which I think should not be )? or Is it decided based on actual VCCIO voltage connected to bank or something else? I will also check on this and will post if I find anything.

Regards,

Bhaumik

Hi Alex and all,

Here is what I was replied by Altera team:

the switching threshold is determined by both the vccio and the i/o standard chosen. if they are mismatched, the functionality is undetermined and we will need to check with the i/o team to see if they can characterize the behavior. some standards (like lvttl) can scale in some (not all) parts, but other standards require specific voltages to function correctly. it really depends on the part and standard chosen...

Thanks to Altera team.

Anyway, as Alex suggested, it's always better ( and safe! ) to choose I/O standard that matches actual VCCIO on board. So while designing Quartus project, we should also consider this. Only assigning pin locations might not be enough.

Have a Great day!:)

Regards,

Bhaumik