Forum Discussion
Altera_Forum
Honored Contributor
12 years agoHi Alex,
Thank you very much for your reply. Unfortunately we are in final stage and might not be able to change Quartus design. Still I will check and if I will be permitted, will make correction. I have few more questions here. Do you have idea how threshold values are being calculated? I mean how FPGA decides what threshold value to be used to decide between '0' and '1'. Is it be according to I/O standard selected in Quartus pin planner ( which I think should not be )? or Is it decided based on actual VCCIO voltage connected to bank or something else? I will also check on this and will post if I find anything. Regards, Bhaumik