Difference float calculation on FPGA and CPU

As long as the floating point operations are carried out in the same order as the CPU code, the output will be exactly the same on the FPGA (a + b + c is not the same as a + c + b or any other permutation of adding these three numbers). Note that parallelizing (including using SIMD) a floating point reduction in an NDRange kernel, or optimizing such operation in a single work-item kernel using a shift register (as outlined in Alrtera's documents) will result in a slightly different output compared to sequential execution on a CPU.