Hi, sorry for the lack of activity here. We are still struggling with these issues and we would like to raise new questions:
- What can be already spotted in the synthesis netlist that can point to us that routing will be difficult? In addition to high-fan-out signals perhaps.
- Can we early detect routing issues in an individual block before it is fully integrated to the complete firmware? How should we do this?
- Is manual floor-planning recommended to address the issues we have? If so, how it should be done?
- Is there a Altera course/material to learn details on the Quartus P&R steps and options, floor planning with practical examples and how they can make routing utilization more efficient, and detailed explanation of the P&R reports?
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