The Global Router Wire Utilization Map and the chip planner gives a visual representation of estimated wire usage on the chip and give detailed information about what might be causing the route congestion.
If the compilation passed and there is no timing violation, there should not be any concern with the routing congestion.
If you want to continue optimize the design, you may checkout the user guide below.
Reference:
https://www.intel.com/content/www/us/en/docs/programmable/683641/24-3/viewing-routing-congestion-in-chip-planner.html
Regards,
Richard Tan
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