Forum Discussion
2 Replies
- Altera_Forum
Honored Contributor
take a look at the synthesis/fit reports, you should be able to find the resource usage by entity or similar
alternatively you can set your HDL at the top level of a QII project and look at the synthesis/fit reports directly - Altera_Forum
Honored Contributor
I typically compile the component as the top level and assign the ports to virtual I/O. This will prevent the fitter from taking my registers and cramming them into the I/O of the device. This will give you a worst case resource utilization number since when your component is in a real system the synthesis engine can perform various packing optimizations with other surrounding logic.