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Altera_Forum's avatar
Altera_Forum
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12 years ago

Design working in simulation not on real device

Hi,

I am trying to design my own implementation of I2C on a Cyclone II EP2C5T144

The design works in simulation but once programmed on the chip, it acts strangely, only a few bits are transfered and they seems incorrect.

I know that this is probably due to signal propagation timing issues, but how to solve that ?

I am a beginner in VHDL designs, and I am open to any suggestions to improve my way of coding.

Thanks for reading me, the files are attached.

Ed

9 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    There are at least two points:

    - 'H' state isn't synthesizable. I2C bus signal must be driven to 'Z' or '0' and use external pull-up resistors. Driving SCL in a push-pull manner is only O.K. if you are sure that the connected slaves don't utilize clock stretching.

    - external signals read into your state machine must be synchronized, by state-of-the-art double registered.
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Hello FvM,

    Thanks for your answer.

    So 'H' (weak pull-up) only works in simulation ? Quartus II should warn about this. I will try with external resistors then.

    I will post the results in the next few days, thanks again for helping.
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Hello,

    I added pull-up resistors but I had no luck with it.

    Then I ran gate level simulation and I got an error :

    # ** Error: (vsim-3601) Iteration limit reached at time 400080 ns.

    How can I solve this issue ? Any clues ?

    Ed
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    iterations limits usually occur when you have some sort of logic loop. Have you run RTL simulation?

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Hi,

    Yes, the RTL simulation is working as expected.

    The error occurs right on state transition. I have also noticed that my "index" variable is decremented in the state before the one it is supposed to be.
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Is this a fully synchronous design? Or does it have asynchronous elements?

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Hi,

    Future state determination is asynchronous as well as the output process. I think that the issue is tied to "index" variable because if instead of decrementing it I set it to a known value, the simulation does not stop. This variable is decremented in the future state determination block.
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    well, if the code is still the same or similar to the code in your first post, you're missing signals from the state machine sensitivity list, so the rtl simulation will be incorrect. you are missing slave_address, register address, RW and data_in. In addition some signals are not assigned values in all cases, creating latches and putting counters inn the async process is casuing the async feedback. Because you're missing signals in the sensitivity list, this is why yopu dont see the problem in the RTL sim. Counters should be in synchronous processes.

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Thanks for your reply Tricky,

    I ended up rewriting the code to be synchronous, seems to be working. I think that my previous approach was not working because my asynchronous future state determination was generating a latch. Now both RTL and gate level simulations are working, I will test it on a real device when I have free time.

    Thanks for your help

    Ed