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Altera_Forum
Honored Contributor
12 years agoThanks for your reply Tricky,
I ended up rewriting the code to be synchronous, seems to be working. I think that my previous approach was not working because my asynchronous future state determination was generating a latch. Now both RTL and gate level simulations are working, I will test it on a real device when I have free time. Thanks for your help Ed