Design working in simulation not on real device

well, if the code is still the same or similar to the code in your first post, you're missing signals from the state machine sensitivity list, so the rtl simulation will be incorrect. you are missing slave_address, register address, RW and data_in. In addition some signals are not assigned values in all cases, creating latches and putting counters inn the async process is casuing the async feedback. Because you're missing signals in the sensitivity list, this is why yopu dont see the problem in the RTL sim. Counters should be in synchronous processes.