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Altera_Forum
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13 years ago

Design with ALTPLL doesn't simulate

I have a very simple design for a Cyclone III in VHDL, which uses a 42MHz input clock to drive the ALLPLL megafunction to generate a 252 MHz clock which then drives a counter. In Quartus 8 with a .vwf , it simulates perfectly well, but in Quartus 12 with Modelsim anda testbench file, everything simulates except the PLL output clock is absent, stuck at 'X'. I've compiled everything in sight and I get no error messages, just no output.

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    ALLPLL needs altera_mf library to be included for simulation. Besides pll needs some time to start clocking.

    Try to create project in MSim add library and simulate from there.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    --- Quote Start ---

    ALLPLL needs altera_mf library to be included for simulation. Besides pll needs some time to start clocking.

    Try to create project in MSim add library and simulate from there.

    --- Quote End ---

    Hi, I went through the tutorial (my company won't run to a training course!) and then created an MSim project and added altera_mf to the search library list. I activate the reset for 200ns. I get the same problem. No clock output from the PLL, even after 1 second of sim-time. Is there something else I should do with the altera_mf library?
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    OK, I changed the way my drive clock was instantiated and now it works. Originally I had it cleared in a one-off process, then toggled in an always process. This seems to leave some sort of 'unknown' in the high state, where it doesn't drive as a forced '1'. Solution seemed to be to initialise the clock in the declaration statement instead. Also shifted the reset pulse to after the start. The altera_mf library was required, so thanks to everybody