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Altera_Forum
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13 years ago

Design with ALTPLL doesn't simulate

I have a very simple design for a Cyclone III in VHDL, which uses a 42MHz input clock to drive the ALLPLL megafunction to generate a 252 MHz clock which then drives a counter. In Quartus 8 with a .vw...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

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ALLPLL needs altera_mf library to be included for simulation. Besides pll needs some time to start clocking.

Try to create project in MSim add library and simulate from there.

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Hi, I went through the tutorial (my company won't run to a training course!) and then created an MSim project and added altera_mf to the search library list. I activate the reset for 200ns. I get the same problem. No clock output from the PLL, even after 1 second of sim-time. Is there something else I should do with the altera_mf library?