Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Design with ALTPLL doesn't simulate

I have a very simple design for a Cyclone III in VHDL, which uses a 42MHz input clock to drive the ALLPLL megafunction to generate a 252 MHz clock which then drives a counter. In Quartus 8 with a .vw...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

OK, I changed the way my drive clock was instantiated and now it works. Originally I had it cleared in a one-off process, then toggled in an always process. This seems to leave some sort of 'unknown' in the high state, where it doesn't drive as a forced '1'. Solution seemed to be to initialise the clock in the declaration statement instead. Also shifted the reset pulse to after the start. The altera_mf library was required, so thanks to everybody