Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Design partition and memory usage

Hi all,

I'm trying to use design partition (now in a top-down flow) but I've a problem.

My ram occupation is about 85% of the device (most of all in 2 block of itself - a coding one and the nios).

The problem is that if I leave the design flat I can compile my design without problems, whereas if I set one of that 2 block as a partion, fitter tells me that it can't fit because "design use 2 MRAM, but will need 4 in order to fit".

I cannot understand what it's happening because if I look at RAM utilization by entity in the flat design and RAM summary in partition merge of the partition one I see that they're exactly the same.

I'm not using the logiclock assignment and I've also tried to tell quartus to use the source files.

The 2 block of memory are logically divided (also they work at different clock) so I don't think they can be shared in some way if Quartus try to synthetize them in one RAM block.

Can I do something or the only solution is not to use design partition?

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    Obviously the easiest thing would be to see your design. but ...

    1 - Could you post all of the compilation messages in a text file? Try looking through the synthesis and fitter warnings to see if there is some other clue.

    2 - In your fitter report you can look at the RAM usage summary which will tell you which RAM blocks are being used by which design entities. If your two design entities are using the same RAM block then you know they are being shared. Because MRAM has two independent ports, it can be shared by two completely different pieces of code.

    3 - What version of Quartus are you using? Supposedly some improvements were mead to design partitioning in 8.0.

    Jake
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    You could target a larger device(with 4 M-RAMs) for the partitioned device(maybe just a Fast Fit). Look at what logical memories get put into the 4 M-RAMs and then see where those logical memories get placed in the flat compile. I'm guessing one of two tings:

    a) Memories are getting merged, which won't happen across partitions. I don't think this is the case since you said they are different clocks, but two single port memories can be put into a single dual-port memory by Quartus

    b) The synthesis of the two partitions both think there are 2 M-RAMs available and use them, but in the flat compile two of those instances get put into smaller RAMs(M9Ks or M4Ks). If this is the case, you want to have thsoe two RAMs target the smaller RAM via the megafunction or in-line synthesis attributes. (I don't know if they're inferred or not) As jakobjones said, the synthesis should be doing a better job if this is the case, and if the latest software version has the problem, it would be worth filing an SR if you can.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    Thx for the replying.

    I've check what Rysc suggested and exactly what happened is that whereas in the flat compilation some part were put into MRAM and others in M512 in the partitioned one all of them were put in MRAM.

    Now I'll change thoose assignment and I'll hope it'll fit (It takes almost 1 h to compile the full design..)

    Thx for the suggestion, I'll let you know if it works

    Edit: Thx that was exactly the problem, now the design fits!