Design partition and memory usage

You could target a larger device(with 4 M-RAMs) for the partitioned device(maybe just a Fast Fit). Look at what logical memories get put into the 4 M-RAMs and then see where those logical memories get placed in the flat compile. I'm guessing one of two tings:

a) Memories are getting merged, which won't happen across partitions. I don't think this is the case since you said they are different clocks, but two single port memories can be put into a single dual-port memory by Quartus

b) The synthesis of the two partitions both think there are 2 M-RAMs available and use them, but in the flat compile two of those instances get put into smaller RAMs(M9Ks or M4Ks). If this is the case, you want to have thsoe two RAMs target the smaller RAM via the megafunction or in-line synthesis attributes. (I don't know if they're inferred or not) As jakobjones said, the synthesis should be doing a better job if this is the case, and if the latest software version has the problem, it would be worth filing an SR if you can.