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Using both edges of same clock in FPGA is problematic and leads to timing paths which cannot or very difficult to define.
Therefore, for my opinion, if you really must use both edges, better practice is to create 2 different posedge clocks with 180 degrees shift between them, using PLL.
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This makes no sense whatsoever. It is perfectly acceptable to use both edges of a clock in FPGAs and it is not necessary to use two separate clocks of opposite phases (if this were true, DDR wouldn't work). If properly constrained, TimeQuest will time all paths properly.
Some suggestions:
- Check your Uncontrained Paths report in TimeQuest. If all your paths are not constrained, then this could be the cause of your failure.
- Check your Ignored Constraints report in TimeQuest. If for some reason any of your constraints are being ignored, you could have failures that you think are being timed properly.
- Run the Design Assistant. If you have any Critical or High Violations, this could be the cause of your failure.
Honored Contributor
