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Altera_Forum's avatar
Altera_Forum
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14 years ago

Design failed on board from time to time

Hi all, I have my design finished and tested on board. But sometimes it works and sometimes it doesn't. My design is a TV data stream scrambling module. It has 7 sub-modules running in p...
Altera_Forum's avatar
Altera_Forum
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14 years ago

I am not saying don't worry about existing violations...

I am saying concluding from results is misleading if violations do occur.

Your clock uncertainty from .3 to 1.2 is not relaxing but more constraining.

I do believe using both edges is problematic but I assume tool will detect timing errors across. However I believe you may pass timing yet sample the data wrongly across edge to edhe transfer. Thus a functional simulation may fail. You may not noticed that unless you use same input pattern.