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Altera_Forum
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14 years ago

Design failed on board from time to time

Hi all, I have my design finished and tested on board. But sometimes it works and sometimes it doesn't. My design is a TV data stream scrambling module. It has 7 sub-modules running in p...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Using both edges of same clock in FPGA is problematic and leads to timing paths which cannot or very difficult to define.

Therefore, for my opinion, if you really must use both edges, better practice is to create 2 different posedge clocks with 180 degrees shift between them, using PLL.