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Altera_Forum's avatar
Altera_Forum
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14 years ago

Design failed on board from time to time

Hi all, I have my design finished and tested on board. But sometimes it works and sometimes it doesn't. My design is a TV data stream scrambling module. It has 7 sub-modules running in p...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Why shouldn't I worry about the existing timing violations?

Because I kinda suspect that setup violation from hiclk to hiclk(the clock domain of the 7 scrambling module) is the reason that caused the failure on board.

Because I used set_clock_uncertainty to hide that violation before, so it actually fails on board. And after the 2nd time I gave a even more relaxed set_clock_uncertainty(from 0.35 of the first time to 1.25), the tool generated a even worse results and yields more failure on board.

SO how could i fix this setup violation?

Thanks a lot!