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Altera_Forum
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14 years ago

Design failed on board from time to time

Hi all, I have my design finished and tested on board. But sometimes it works and sometimes it doesn't. My design is a TV data stream scrambling module. It has 7 sub-modules running in p...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

kaz, I have observed my failure happened just when it's data should be scrambled by the 5th and 6th module(and their occurence in different trials are nondeterministic). So I suspect there could me some timing problem there.

And I just tuned my sdc file a little bit. I used to set_clock_uncertainty from hiclk to hiclk 0.35 to get rid of some setup violation. And after I have changed 0.35 to 1.24, I've found my error pattern changed. Now I got my errors occur more often and they are not restricted to 5th and 6th module scrambled data anymore.

Do you think I should've avoided using set_clock_uncertainty?