Altera_ForumHonored Contributor14 years agoDesign failed on board from time to time Hi all, I have my design finished and tested on board. But sometimes it works and sometimes it doesn't. My design is a TV data stream scrambling module. It has 7 sub-modules running in p...Show More
Altera_ForumHonored Contributor14 years agoAlso - did you specify timing specs or did you just look at the FMAx calculation?
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