Here's more information: Before the compilation with Quartus 23.1.1 quits the following messages are shown: "Info (276014): Found 1 instances of uninferred RAM logic" and "Info (276007): RAM logic "memory:i_memory|ram16k:i_ram16k|ram_s" is uninferred due to asynchronous read logic".
The VHDL code that causes these messages is the following:
entity ram16k is
port (
clk : in std_logic;
i : in std_logic_vector(15 downto 0);
load : in std_logic;
address : in std_logic_vector(13 downto 0);
o : out std_logic_vector(15 downto 0)
);
end ram16k;
architecture behavior of ram16k is
type ram_t is array(0 to 16383) of std_logic_vector(15 downto 0);
signal ram_s : ram_t := (others =>(others => '0'));
begin
o <= ram_s(to_integer(unsigned(address)));
process (clk)
begin
if (falling_edge(clk) and load = '1') then
ram_s(to_integer(unsigned(address))) <= i;
end if;
end process;
end behavior;
The RAM of the "From Nand-To-Tetris"-system has such an asynchronous read. Quartus 17.0.0. inferred this with the message "276020 Inferred RAM node ... from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design".
Is there a way to configure Quartus 23.1.1, to do this in the same way?
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