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SKon1
Occasional Contributor
Occasional Contributor"derive_pll_clocks" doesn't create generated clocks properly
"derive_pll_clocks" doesn't create generated clocks properly Hello, In my Arria V design. I have a PLL with one input and 3 outputs. The input is 125 MHz. The outputs are as follows: 1. Output 0 ...
SKon1Occasional Contributor
Occasional ContributorUpdate - I was able to solve it myself using information from this link:
https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/solutions/rd03062013_146.html
However,
I'm now encountering problems to meet timing.
Please help me with this:
https://forums.intel.com/s/question/0D50P00004eYylhSAC/intel-rgmii-example-output-delay-failure
