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SKon1's avatar
SKon1
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

"derive_pll_clocks" doesn't create generated clocks properly

"derive_pll_clocks" doesn't create generated clocks properly Hello, In my Arria V design. I have a PLL with one input and 3 outputs. The input is 125 MHz. The outputs are as follows: 1. Output 0 ...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,

Can you share the design for investigation? What is the edition (Pro/Standard) and version you are using?

Thanks.

Best regards,

KhaiY